1. Field of the Invention
The present invention relates to a standby current erasure circuit applied in DRAM, more particularly to a circuit for erasing the short DC standby current between the complementary bit lines and the word lines of DRAM.
2. Background of the Invention
In the manufacturing process of DRAM, a short circuit between the bit line and the word line sometimes occurs and causes a leakage current and affects the product yield.
One of the solutions for the above-mentioned problem is disclosed in U.S. Pat. No. 5,499,211, entitled xe2x80x9cBIT-LINE PRE-CHARGE CURRENT LIMITER FOR CMOS DYNAMIC MEMORIES.xe2x80x9d As shown in FIG. 1, a conventional circuit 10 comprises a word line 12, a pair of complementary bit lines 13, a pre-charge equalizing circuit 14 and a current-limiting means 11. In prior art, in order to prevent an excess leakage current caused by the short circuit between the bit line (WL) and the word line (BL), a current-limiting means 11, such as a depletion NMOS, is added between a source of pre-charge voltage (VBLEQ) 15 and the pair of complementary bit lines 13 so as to limit the maximum leakage current when the short circuit between the bit line and the word line occurs.
Generally, the word line voltage (VWL) is 0 volt in the standby mode, but the bit line voltage is larger than 0 volt. Thus, a leakage current path will be formed in the standby mode. The leakage current will flow from BLEQ, BL, WL to the ground. In other words, the conventional method cannot effectively reduce the leakage current when the short circuit between the bit line and the word line occurs. For the current application in the product for low power DRAM, the leakage current is still too large to satisfy the market requirement.
Regarding the problems in the prior art, the present invention provides an innovative standby current erasure circuit for the DRAM to overcome the above-mentioned disadvantages.
The object of the present invention is to provide a two-phase pre-charge circuit and its short DC standby current erasure circuit of DRAM, which is suitable for the application requirement in a low power DRAM.
To this end, the present invention discloses a two-phase pre-charge circuit which is only activated during the active mode of the DRAM for electrically connecting the source of pre-charge voltage and the complementary bit lines. In the standby mode of the DRAM, the two-phase pre-charge circuit is in a disablement state, thereby the short DC standby current between the complementary bit lines and word lines is erased.
The standby current erasure circuit for DRAM according to the present invention comprises a pre-charge equalization circuit and at least one control signal. One end of the pre-charge equalization circuit is connected to the source of pre-charge voltage and the other end is connected to the complementary bit line. The at least one control signal is used to generate one pulse in the beginning and end of the active mode of the DRAM for electrically connecting the source of pre-charge voltage and the complementary bit line, and the at least one control signal is disabled in the standby mode of the DRAM.